The present invention relates generally to very large scale integrated (VLSI) circuits, Systems on a Chip (SOC), and more particularly to group based integrated circuit design methodologies and integrated circuits developed using group based design methodologies.
Advances in integrated circuit technology allow for the production of integrated circuit semiconductor devices having millions of gates, with each of the gates made up of multiple transistors. These semiconductor devices perform an array of tasks, some of which are exceedingly complex.
The complexity of the tasks performed by the devices has resulted in part from advances in the capabilities of design related tools, many of which are concerned with the synthesis of designs from a high level description language to a register transfer level description, and then to low level circuit elements. These tools often reduce the amount of detail a designer must determine to design an integrated circuit. In many instances, the tools determine, based on the input of a designer and predetermined rules, many of the details of the design. The tools therefore, at least theoretically, reduce the effort required to design an integrated circuit.
These design tools therefore assist designers in managing the complexity of integrated circuits. To an extent, design tools abstract the design of the integrated circuits, as well as the processes used to test, verify and implement the circuits. This abstraction reduces the amount of detail required to be specified and understood by designers. This abstraction, accordingly, may allow a design team to implement a device whose complexity may otherwise overwhelm the capabilities of the design team.
For example, in an ideal case the designer merely specifies behavior, using an HDL, such as Verilog, or VHDL or the like. Complex tools translate the specified behavior through numerous stages. This translation, or transformation, often synthesizes a high level description to an RTL model, and then synthesizes the RTL model to a cell or gate level description. The tools also sometimes verifies the correctness of the translations, and also provides a physical layout of transistors or gates, and signal paths interconnecting the transistors or gates, to implement the specified behavior.
Unfortunately, the use of such tools often introduce some inefficiencies and inconsistencies from desired behavior. For example, the tools often partition the design into relatively low level constituent parts. The low level constituent parts are then mapped into relatively low level circuits, often approximating the logic gate level. The partitioning and mapping, as well as the low level constituent parts, are often somewhat generalized, and are not optimized to perform specific tasks. The resulting circuit or system is therefore sometimes inefficient in terms of power, performance or area usage.
In addition, the tools often use a set of heuristics to automatically determine signal routing among the relatively lower level circuits. The use of automatic routing may have several unintended results. For example, automatic signal routing may result in unexpectedly long signal paths, requiring the use of increased power by driver circuits. Also the use of statistical wire load models can introduce incorrect timing information, resulting in timing closure problems.
Thus, while in some cases the use of such design tools may allow for decreased design time, the use of the tools may often result in inefficient physical designs in terms of size, performance, and power. The designs are inefficient because the gate or transistor count is not optimized, and the signal routing is awkward. Accordingly, the use of such design tools would appear to require a trade-off of increased circuit power and size utilization for decreased design time.
Unfortunately, the use of such design tools may also inadvertently result in lengthened design cycles. For example, when using synthesis, signal degradation may occur or out of budget clock skew may result, because of cross-talk (sometimes called signal integrity). It may be difficult to detect this signal interference due to cross-talk, and determining timing problems may be difficult. Moreover, these inefficiencies may be particularly pronounced for devices operating at high clock speeds, which are often more susceptible to timing problems, and devices built with deep submicron technologies, which often are more susceptible to signal cross-talk.
In addition, the use of machine chosen circuit elements and circuit routing makes error resolution difficult in that the circuit layout may not be intuitively understood or understandable by the designer or the person doing the debugging. For example, each synthesis operation transforms the design, and may do so for the complete design in a global fashion. Such a transformation may result in an unoptimized, difficult to comprehend design. In the event of errors such a design is likely to be difficult to debug. Thus, as circuit complexity increases and as the circuit geometry decreases, circuit debugging is difficult to do and timing closure becomes more difficult to obtain.
For many years in the prior art, libraries have been constructed that allow direct implementation of primitive Boolean functions. Typically these libraries consist of AND, OR, NOR, NAND, XOR, flip-flops and the like. The term “cell” is almost universally applied to such approach, a library of cells, called “cell library” is often referred to as the basic building blocks for more complex circuit designs. Sometimes these elements of a cell library implemented multiple Boolean functions in one cell to provide a more complex Boolean expression. An example is AOI (AND/OR/INVERT).
In another approach to providing complex functionality, beginning in about the early 1960's, microcode was widely used to implement computer instructions. Commonly used sequences of instructions were kept together and reused in other programs or decoding schemes. These sequences were called “Macros” or Macrocode. Later, the term Macro began to be used to describe a larger grouping of cells from the cell library, typically 4 or 5 cells combined in a “super cell” or macro. These small number of cells provided a small productivity improvement for the designer.
A further approach to complex circuit design popularized in about the 1980's is the gate array. Gate arrays were used heavily, and it became common for the gate array design service to provide a cell library of Boolean primitives, as well as macros. These macros typically contained on the order of 10 to 20 gates. By the mid-1980's cell libraries became quite complex to support new synthesis tools. Some cell libraries contained 50 to 100 cells. To make synthesis more efficient cell libraries of 500 to 1000 cells have been developed. Each cell usually contains only 1 to 10 gates, but have varying power levels and many combinations of inverting capability.
Today, cell libraries continue to exist, and are used for all Standard Cell, Gate Array and Embedded Array designs. Macro's are still in use but are primarily for use in conjunction with FPGA's and CPLD's, and are still composed of a small number of gates. The large electronic design automation vendors, often use the terms macros, cores and IP as synonymous. In fact the RMM book from Synopsys and Mentor Graphics define them as being the same as a “Block.” Usually a block is defined as a 50,000 to 200,000 gates of logic. In many cases today IP or cores are blocks that describe a function such as a PCI core or a register file or a memory. Thus a core, or IP, tends to be functionally oriented and is usually larger than 50,000 gates. These cores or blocks can be hard or soft, where hard is in physical form and soft is in logical form, typically RTL.
Thus what is needed is a more efficient approach to the design of complex circuits or systems, which allows the designer to combine larger numbers of circuit cells or gates into a significant enough amount of circuitry that enables easier design of complex functionality, but which is also reusable for other designs. At the same time the combination yields higher performance, reduced circuit area, lower power, and improved productivity compared to prior art approaches.